Additionally double clicking an output netlist entry in the netlister highlights wires in the schematic that created the net. This allows the designer to check that the netlist is correct by providing feedback from the netlister to the schematic.
DipTrace Schematic Capture and PCB Layout also support popular netlist formats and spice. Output formats are DXF, Gerber, Drill and G-code. Standard libraries include 100.000+ components.
Features : Verilog simulator and debugger, supporting full IEEE 1364-2001 Verify behavioral and RTL models with functional simulation Verify pre/post-layout gate-level netlist with SDF back-annotation timing simulation