Simple Solver (SSolver) provides a suite of five design tools: Boolean, Permutation, Random Number, Simulation and Logic Design. These tools can be used to minimize, simplify and reduce logic equations and digital logic circuits.

Booleans
The Boolean function provides minimization and truth tables for one or a series of Boolean equations. Operator formats are supported for a variety of languages including: ABEL, C, C++, PALASM, Verilog, VB and VHDL. The Boolean minimizer uses a Karnaugh map approach, also known as a Veitch diagram.

Permutations
The Permutation function (PERM) calculates permutations of numbers for a specified number of digits and width. PERM can be used for a variety of applications such as generating binary, octal or decimal number tables.

Random Numbers
The Random Number function produces random sequences of numbers in the range of -9999 to 9999. It can be used for many purposes: shuffling 52 numbers (like a deck of cards), randomly selecting a subset of operations for sample testing, and so forth.

Logic Simulation
The Simulation function (SIM) provides simulation of user-specified digital logic circuits. SIM can be used to evaluate both circuit functionality and timing problems such as flip-flop setup and hold times, race conditions and glitches/spikes.

Logic Design
The Synthesis function (SYN) provides automatic design and simulation of digital logic circuits from truth table or waveform inputs. All circuit types and configurations are supported: Combinational, Sequential, Synchronous and Asynchronous. SYN performs automated logic design by searching for circuits that provide the transfer function specified by the input and output signal waveforms. In general, the first circuit solution found will be the simplest possible solution.

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